1. Field of Invention
The present invention relates to a timing adjustment device and method. More particularly, the present invention relates to a bus interface timing adjustment device, method and application chip.
2. Description of Related Art
Due to increasing complexity of circuit boards, proper design of trace lines linking various devices and the processing of timing signals between different devices is increasingly difficult. In general, the chip manufacturer will provide necessary AC timing signals for synchronizing various devices on an integrated chip. However, due to difference in conditions of silicon chip manufacturing, trace layout or method of producing the printed circuit board (PCB), accuracy of the timing signal is often compromised.
Using the computer as an example, most computer systems are comprised of a central processing unit (CPU), a north bridge device and a south bridge device (the north bridge device and the south bridge device together constitute a control chipset, or chipset in short). The central processing unit is coupled to the north bridge device. The north bridge device and the south bridge device are connected together through a high-speed bus. The north bridge device also exercises control over high-speed dynamic random access memory (DRAM). Principle function of the south bridge device includes controlling peripheral devices. The central processing unit and the north bridge device access data via a system bus. Similarly, the south bridge device and the north bridge device access each other's data through the control chipset bus. The north bridge device controls the high-speed dynamic random access memory through a memory bus. Hence, when the central processing unit and the north bridge device as well as the south bridge device and the north bridge device are conducting some data transactions, any mismatch in the trace line of circuit may lead to timing deviation. Serious timing deviation may result in data access errors and system instability. At present, however, most north bridge devices and south bridge devices have no special features for making timing and boost-signal driver adjustment. Thus, whenever there is a timing mismatch that results from a difference in chip property, printed circuit board layout and quality due to surface mount technology (SMT), trace lines for the circuit board must be re-routed again leading to an increase in production time and cost.
Furthermore, the clocking signal received by the memory of a computer system deviates according to the number of dual memory modules and the number of memory chips on the dual memory module plugged into the system. Hence, gauging the timing variation between the memory and the memory control device is very difficult. Because of this, the memory control device often has a register especially reserved for adjusting the timing at the memory interface. Yet, the adjusting value inside the register is normally stored as a fixed value inside the basic input/output system (BIOS) and that value is difficult to change. To counteract differences due to manufacturing by various wafer manufacturers, differences due to bus layout on printed circuit boards and differences due to surface mount technologies, the adjusting value must be changed according to the actual conditions. This arrangement is not only cumbersome, but also leads to frequent inaccuracies. Another method is to provide a buffer to serve as an internal delay for clocking signal for adjusting the timing signals. However, this method can delay the phase of internal clocking signals only. Since there is no way to push the phase of the internal clocking signal forward, this method can have only limited accuracy.